Networks are key components of all computer and communication systems. High performance networks use point-to-point links rather than shared media, in order to exploit parallelism and avoid turn-around and arbitration delays. These networks are built out of packet switches or routers, interconnected by point-to-point links. Gigabit networking requires high speed switches and routers, fast computer-network interfaces, advanced quality-of-service and flow control architectures, and sophisticated systems software.
Among other R&D topics, the Computer Architecture and VLSI Systems (CARV) Division of ICS-FORTH has also been very active in research and development work on Packet Switch and Router Architecture, since 1985, as described below; for further details, follow the links at the topic headings.
Pipelined Memory: it is a novel, patented organization that we designed (1993-95) for the shared buffer and associated switching and cut-through functions in a switch or router. It is simpler and smaller than other alternative organizations, and is particularly suited for VLSI technologies. We have used it in the "Telegraphos" and "ATLAS" switches. FORTH owns the USA patent 5,774,653 on the pipelined memory shared buffer switch.
ATLAS I, a 10 Gbit/s single-chip ATM switch with backpressure: this 6-million-transistor 0.35-micron CMOS chip was designed in CARV, ICS-FORTH (1995-98). It provides sub-microsecond cut-through latency, credit-based flow control (multilane backpressure), logical output queues in a shared buffer, 3 priority levels, multicasting, and load monitoring. This general-purpose building block for gigabit networking was fabricated by ST Microelectronics, and was developed in collaboration with Intracom, BULL, Telenor, Telefonica, and others.
Per-Flow Queueing. The provision of QoS guarantees by modern, advanced-architecture network systems requires the differentiation of traffic into multiple flows, and the isolation among them by providing a separate queue for each. Managing so many (hundreds or thousands to possibly millions) queues at high speed typically requires the assistance of specialized hardware. We have worked on such multi-queue management implementations at different cost and performance levels.
Weighted-Round-Robin Scheduling. After the competing flows have been isolated using per-flow queueing, fairly allocating the available bandwidth to them requires a weighted-round-robin scheduler. We have investigated in detail various methods to perform this, at different cost and performance levels, starting in 1986 (IEEE JSAC Oct. 1987, pp. 1315-1326), and continuing with our current work on pipelined heap management for weighted fair queueing at the rate of 20 to 40 Gbps.
Multilane Backpressure (Credit-Based Flow Control): we proposed its use in LANs and WANs in IEEE JSAC, October 1987, and then used it in our "Telegraphos" and ATLAS I switches.
Wormhole IP over ATM. To enable low-cost internetworking at gigabit rates, we were among the first to propose and analyze this technology. It is inspired from the wormhole-routing multiprocessor interconnection networks of the 80's, and it allows one to turn existing ATM networks into gigabit IP routers (in addition to serving the normal ATM traffic), with the mere addition of low-cost wormhole-IP devices; IP routing delay is minimized, owing to virtual cut-through forwarding of the ATM cells. We are currently testing an FPGA-based prototype for a bi-directional 155 Mbps link.