Institute of Computer Science, FORTH, Heraklion, Crete, Greece.
A Brief Overview of the:

Computer Architecture and VLSI Systems Division

Computer Architecture and VLSI Systems (CARV) deals with the architecture, design, and implementation of hardware and systems software for digital computer and communication systems. CARV is one of the five R&D divisions of the Institute of Computer Science (ICS), FORTH, closely collaborating with the Department of Computer Science of the University of Crete. The goals of the Division are to:

CARV is staffed by approximately: The people in the Division use and are experienced with the following tools:

In research and development, emphasis is currently on high-speed networking, since this is the fastest-evolving area of digital system architecture. Gigabit networking is the key to a whole set of new application areas: Information Superhighways, the Internet, the Web, Multimedia Systems, Networks of Workstations (NOW), and High Performance Computing and Networking (HPCN). Gigabit networking requires high speed switches and routers, fast computer-network interfaces, advanced quality-of-service and flow control architectures, and sophisticated systems software.

Gigabit Switching: CARV completed recently the development of ATLAS I, a 10 gigabit-per-second, single-chip ATM switch. This 6-million-transistor 0.35-micron CMOS chip provides sub-microsecond cut-through latency, credit-based flow control (multilane backpressure), logical output queues in a shared buffer, 3 priority levels, multicasting, and load monitoring; it uses our pipelined memory architecture (USA patent 5,774,653). This general-purpose building block for gigabit networking is being fabricated by ST Microelectronics, and was developed in collaboration with Intracom, BULL, Telenor, Telefonica, and others.

Quality-of-Service (QoS): the Division is active since 1985 on key technologies for advanced QoS architectures: per-flow queueing, round-robin scheduling, and multilane backpressure. Recently, we designed FPGA-based prototypes that demonstrate high-speed management, in hardware, of thousands of queues (per-flow queueing) and weighted-round-robin scheduling of thousands of flows. Current interest is in pipelined heap management for multi-gigabit weighted fair queueing.

IP over ATM: To enable low-cost internetworking at gigabit rates, CARV was among the first to propose and analyze Wormhole IP over ATM. This technology, inspired from the wormhole-routing multiprocessor interconnection networks of the 80's, allows one to turn existing ATM networks into gigabit IP routers (in addition to serving the normal ATM traffic), with the mere addition of very-low-cost wormhole-IP devices; IP routing delay is minimized, owing to virtual cut-through forwarding of the ATM cells. We are currently building an FPGA-based prototype for a bi-directional 155 Mbps link.

Multimedia, Security, Real-Time: The Division is active in high-speed network architectures for a wide range of applications, using modern technology: (i) support for real-time (e.g. multimedia) applications; (ii) security architectures and systems; (iii) crossbar scheduling for advanced input queueing; (iv) exploitation of emerging technologies, like embedded systems, real-time operating systems, etc.

Past work in hardware includes the following:

  • data logging, step-motor controller (1986, prototypes built);
  • microcontroller for managing UPS loads (1989, system built);
  • branch penalty reduction in pipelined processors (1990);
  • parallel supercomputer architecture (1991-94);
  • high-speed UART macrocell (1991, chip & board implemented);
  • Sbus-to-TAXI interface (1992, chip design);
  • controller for a VHF system (1993, chip implemented);
  • interleaved Rambus memory controller (1994, chip design);
  • JPEG entropy encoder (1994, chip implemented);
  • Telegraphos I network adapter (1995, multi-FPGA board implemented);
  • Telegraphos I switch (1995, multi-FPGA board implemented);
  • Telegraphos II switch (1996, chip & test board implemented);
  • pipelined memory demonstrator (1995, full-custom chip implemented);
  • PCI/i960 based systems, and device drivers for them (1997-98);
  • SDRAM high-throughput buffer for switches (1998, FPGA board implemented);
  • superscalar embedded microcontroller architecture (1998).

    Workstation Clustering: A project recently completed was the design and implementation of Telegraphos, a high-performance workstation cluster, that turns a set of workstations into a high-performance computing system. The novel features of Telegraphos include user-level DMA, fast message arrival notification (patent application), and low latency communication. System software was developed that allows any application on any workstation to exploit all available resources (memory, processors, disks) in a workstation cluster:

  • remote memory paging systems
  • fault-tolerant main memory databases
  • fault-tolerant main memory file systems.
    Within Telegraphos we also designed and built parallel applications. CARV has considerable expertise in parallelizing sequential programs and optimizing them to run on a variety of parallel and distributed architectures. We have used a variety of platforms, including KSR-1, Silicon Graphics shared-memory multiprocessors, the BBN Butterfly, and workstation clusters connected with FDDI, ATM and SCI.

    Web Caching and Searching: To reduce the long latency experienced by most users of the world wide web we have developed novel caching and prefetching mechanisms that allow web files to be kept in a storage place close to end users. They can reduce client latency, reduce network traffic, and increase the net profit of cache operators. CARV is currently working on searching, resource discovery, and visualization tools for the world wide web. Existing search engines often reply with a flood of URLs; when one only seeks new information on a topic previously searched, one still receives the same flood of all relevant URLs. This latter style of "re-search" --staying up-to-date in a field, finding "what's new"-- is not provided by current search engines. To support it, we devised a methodology for persistent searching, and we implemented tools (USEwebNET, PaperFinder) that persistently monitor databases to find items that match a user's profile; items found are presented via a user-friendly interface.

    Architectural CAD: One of the Division's activities is to provide training courses and expert services in CAD for engineering, and especially in computer aided architectural design of buildings.

    Past work includes also the development (1989-93) of the Labyrinth System --a general-purpose object-oriented core for the graphical editing of parameterized, interconnected designs.

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    © copyright ICS-FORTH, Crete, Greece.
    Last updated: December 1998, by M. Katevenis.