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a 10 Gbit/s ATM Switch Chip with Credit Flow Control
1. What is ATLAS I
ATLAS I (ATm multi-LAne backpressure Switch One)
is a single-chip gigabit ATM switch
with optional credit-based (multilane backpressure) flow control.
This 6-million-transistor 0.35-micron CMOS chip offers:
10 Gbit/s outgoing throughput,
sub-microsecond cut-through latency,
256-cell shared buffer containing multiple logical output queues,
priorities, multicasting, VP/VC translation,
advanced flow control architecture, and load monitoring.
It is a general-purpose building block
for high-speed communication in
wide (WAN), local (LAN), and system (SAN) area networking,
supporting a mixture of services
from real-time, guaranteed quality-of-service
to best-effort, bursty and flooding traffic,
in a range of applications
from telecom to multimedia and multiprocessor NOW.
2. Who develops ATLAS I
ATLAS I is designed in the
Computer Architecture and VLSI Systems Division,
Institute of Computer Science (ICS),
Foundation for Research & Technology - Hellas (FORTH),
Science and Technology Park of Crete (STEP-C),
ATLAS I is being developed within the
funded by the European Union
The ASICCOM Consortium consists of industrial partners
SGS THOMSON, France and Italy;
and research institutes
Poli. di Milano, Italy;
3. Contact Point
For further information, beyond what is available below,
please contact Prof.
ICS-FORTH, Vassilika Vouton,
P.O. Box 1385, Heraklion, Crete, GR 711 10 Greece.
Tel: +30 (81) 39.16.64; Fax: +30 (81) 39.16.61
4. Reading List
For more information on ATLAS I,
please refer to the following documents.
These are divided in three categories:
general overview and architecture of ATLAS I,
methods to use ATLAS I and take advantage of its features, and
implementation of ATLAS I.
Within each category, documents are listed in order of
increasing depth and detail.
(Members of the ASICCOM Consortium also have access to a number of
that are not yet stable enough to be made public).
4.1 General Overview and Architecture of ATLAS I
General overview in plain text (2 pages):
lists the features of ATLAS I
and briefly discusses ways to exploit
its credit-based (multilane backpressure) flow control.
Transparencies of a General Overview Talk on ATLAS I
``ATLAS I: A General-Purpose, Single-Chip ATM Switch
with Credit-Based Flow Control''
(by M. Katevenis, D. Serpanos, P. Vatsolaki),
Proc. Hot Interconnects IV Symposium,
Stanford Univ., CA, USA, Aug. 1996, pp. 63-73.
A good detailed introduction to ATLAS I,
appropriate as first reading on this switch
(11 pages, 63 KB gziped Postscript).
4.2 Using ATLAS I and taking Advantage of its Features
``Switching Fabrics with Internal Backpressure
using the ATLAS I Single-Chip ATM Switch''
(by M. Katevenis, D. Serpanos, E. Spyridakis),
Proc. GLOBECOM'97 Conference,
Phoenix, AZ, USA, Nov. 1997, pp. 242-246.
Explains the use of ATLAS' credit flow control
inside large switch "boxes",
to provide the high performance of output queueing
at the low cost of input queueing,
while any desired flow control method is employeed outside the box
(6 pages, 52 KB gziped Postscript).
``Credit-Flow-Controlled ATM for MP Interconnection:
the ATLAS I Single-Chip ATM Switch''
(by M. Katevenis, D. Serpanos, E. Spyridakis),
Proc. 4th Int. Symp. on High-Perf. Computer Arch. (HPCA-4)
Las Vegas, NV, USA, Feb. 1998, pp. 47-56.
Argues that ATM extended with credit-based flow control
has notable similarities to wormhole routing,
the popular multiprocessor interconnection network architecture.
Then, it compares the credit protocol of ATLAS I (similar to QFC)
to the wormhole backpressure protocol,
and shows why the former performs quite better.
Together with the GLOBECOM'97 paper above,
this paper offers a new perspective on the merits of
switching fabrics, SAN's, LAN's, or entire sub-networks
that employee internal backpressure (credit flow control)
(11 pages, 57 KB gziped Postscript).
Transparencies of this Talk at HPCA-4
``Admission Control and Routing in ATM Networks
using Inferences from Measured Buffer Occupancy''
(by C. Courcoubetis, G. Kesidis, A. Ridder, J. Walrand, R. Weber),
IEEE Trans. on Communications,
vol. 43, no. 4, April 1995, pp. 1778-1784.
Describes a method for the accelerated measurement
of the cell loss probability (CLP) of the real traffic
that passes through a switch;
this allows real-time monitoring and decision making,
even in cases where the CLP is so low
that normal measurement methods
would require too long a measurement time;
ATLAS I provides the hardware support
for such accelerated measurement
(7 pages, 208 KB Postscript).
are also available (html/gif).
4.3 Implementation of ATLAS I
The papers listed above more or less suffice
to cover all published aspects of ATLAS I.
For other published papers, on ATLAS I and on other projects,
see the detailed
of the Computer Architecture and VLSI Systems Division.
``Implementation of ATLAS I:
a Single-Chip ATM Switch with Backpressure''
(by G. Kornaros, D. Pnevmatikatos, P. Vatsolaki, G. Kalokerinos,
C. Xanthaki, D. Mavroidis, D. Serpanos, M. Katevenis),
Proc. IEEE Hot Interconnects VI Symposium,
Stanford, California, USA, Aug. 1998.
A slightly shorter version of this paper appears in
IEEE Micro, vol. 19, no. 1, Jan/Feb. 1999, pp. 30-41,
under the title
``ATLAS I: Implementing a Single-Chip ATM Switch with Backpressure''.
Reports on the design complexity and silicon cost of ATLAS I
and of the individual functions that the chip supports.
Based on these metrics,
we evaluate the architecture of the switch.
We also show that the cost of credit support
(10% in chip area and 4% in chip power)
is minuscule compared to its benefits.
(Available in HTML or Postscript; 12 pages).
``Pipelined Multi-Queue Management in a
VLSI ATM Switch Chip with Credit-Based Flow Control''
(by G. Kornaros, C. Kozyrakis, P. Vatsolaki, M. Katevenis),
Proc. 17th Conf. on Adv. Research in VLSI (ARVLSI'97),
Univ. of Michigan at Ann Arbor, MI USA, Sept. 1997, pp. 127-144.
Describes the implementation of the queue management block,
the heart of ATLAS' control section
--a dual parallel pipeline that manages
the multiple queues of ready cells,
the per-flow-group credits,
and the cells that are waiting for credits;
special emphasis is placed on the full-custom part of queue management,
including the content-addressable and priority blocks in it
(13 pages, 94 KB gziped Postscript).
``The Memory Structures of ATLAS I,
a High Performance, 16x16 ATM Switch Supporting Backpressure''
(by D. Pnevmatikatos, G. Kornaros, G. Kalokairinos, C. Xanthaki),
Proc. of the 11th Annual IEEE Intnl. ASIC Conf. (ASIC'98),
Rochester, NY, USA, Sept. 1998, pp. 23-27.
Describes in detail the memory structures of ATLAS I.
First presents the requirements posed by the architecture,
and then presents the solutions used in its implementation.
Where the actual implementation was limited by our design environment,
we propose alternative, more efficient possible implementations.
(5 pages, 125 KB gziped Postscript).
``Pipelined Memory Shared Buffer for VLSI Switches''
(by M. Katevenis, P. Vatsolaki, A. Efthymiou),
Proc. ACM SIGCOMM '95 Conference,
Cambridge, MA USA, Aug. 1995, pp. 39-48.
Describes the pipelined memory organization,
which is used for the (shared) cell buffer of ATLAS I
(Patent Application pending
(European 95410074.9, USA 08/506019); August 1994)
(10 pages, 81 KB gziped Postscript).
``ATLAS I: A Single-Chip ATM Switch with
HIC Links and Multi-Lane Back-Pressure''
(by M. Katevenis, P. Vatsolaki),
Proc. EMSYS 96 Conf. (ESPRIT OMI: Embedded Microprocessor Systems),
Berlin, Germany, Sept. 1996, IOS Press, ISBN 90 5199 300 5, pp. 126-136.
Describes ATLAS I, with particular emphasis on the
physical/datalink layer used by the chip (IEEE Std. 1355 ``HIC/HS'')
and why and how multilane backpressure was added
as an optional extension
on top of the single-lane backpressure provided by the 1355 standard
(11 pages, 42 KB gziped Postscript).
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Computer Architecture and VLSI Systems Division of ICS-FORTH.
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Last updated: February 1999, by