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a 10 Gbit/s ATM Switch Chip with Credit Flow Control

[ATLAS I feature overview figure]

1. What is ATLAS I

ATLAS I (ATm multi-LAne backpressure Switch One) is a single-chip gigabit ATM switch with optional credit-based (multilane backpressure) flow control. This 6-million-transistor 0.35-micron CMOS chip offers: 10 Gbit/s outgoing throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, VP/VC translation, advanced flow control architecture, and load monitoring. It is a general-purpose building block for high-speed communication in wide (WAN), local (LAN), and system (SAN) area networking, supporting a mixture of services from real-time, guaranteed quality-of-service to best-effort, bursty and flooding traffic, in a range of applications from telecom to multimedia and multiprocessor NOW.

2. Who develops ATLAS I

ATLAS I is designed in the Computer Architecture and VLSI Systems Division, of the Institute of Computer Science (ICS), Foundation for Research & Technology - Hellas (FORTH), in the Science and Technology Park of Crete (STEP-C), in Heraklion, Crete, Greece.

ATLAS I is being developed within the ASICCOM Project, funded by the European Union ACTS Programme. The ASICCOM Consortium consists of industrial partners (INTRACOM, Greece; SGS THOMSON, France and Italy; BULL, France), telecom operators (TELENOR, Norway; TELEFONICA, Spain), and research institutes (FORTH, Greece; SINTEF, Norway; Poli. di Milano, Italy; Democritos, Greece).

3. Contact Point

For further information, beyond what is available below, please contact Prof. Manolis Katevenis, ICS-FORTH, Vassilika Vouton, P.O. Box 1385, Heraklion, Crete, GR 711 10 Greece.
E-mail: katevenis@ics.forth.gr; Tel: +30 (81) 39.16.64; Fax: +30 (81) 39.16.61

4. Reading List

For more information on ATLAS I, please refer to the following documents. These are divided in three categories: (i) general overview and architecture of ATLAS I, (ii) methods to use ATLAS I and take advantage of its features, and (iii) implementation of ATLAS I. Within each category, documents are listed in order of increasing depth and detail. (Members of the ASICCOM Consortium also have access to a number of working documents that are not yet stable enough to be made public).

4.1 General Overview and Architecture of ATLAS I

4.2 Using ATLAS I and taking Advantage of its Features

4.3 Implementation of ATLAS I

The papers listed above more or less suffice to cover all published aspects of ATLAS I. For other published papers, on ATLAS I and on other projects, see the detailed publications list of the Computer Architecture and VLSI Systems Division.

Up to the Computer Architecture and VLSI Systems Division of ICS-FORTH.
Up to the Institute of Computer Science (ICS) of FORTH, in Heraklion, Crete, Greece.
Up to the ASICCOM Project Home Page.
© copyright ICS-FORTH, Crete, Greece.
Last updated: February 1999, by M. Katevenis.